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verilator - A fast simulator for synthesizable Verilog
- Description:
Verilator is the fastest free Verilog HDL simulator. It compiles
synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis
assertions into C++ or SystemC code. It is designed for large projects
where fast simulation performance is of primary concern, and is
especially well suited to create executable models of CPUs for
embedded software design teams.
Packages
| verilator-3.890-1.fc24.x86_64
[3.1 MiB] |
Changelog
by Filipe Rosset (2016-11-28):
- Rebuilt for new upstream version 3.890
- Spec clean up plus fixes rhbz #1087393 and rhbz #1358609
|